LPDDR6 vs LPDDR5X: The 24-Bit Channel and Bandwidth Math

The biggest difference between LPDDR6 and LPDDR5X is not speed but channel width. A channel that stayed 16 bits wide for over a decade is now 24 bits, and that 24-bit channel splits into two independent 12-bit sub-channels. The JESD209-6 specification, published by JEDEC on July 9, 2025, defines a data rate range of 10,667 to 14,400 MT/s.

On raw speed alone that is 1.69 times the 8,533 MT/s JEDEC ceiling for LPDDR5X. But the bus also got 1.5 times wider, so per-channel bandwidth more than doubles. That multiplication is what lies behind Tom's Hardware describing it as "double the effective bandwidth of current gen."

Run the published specs through the arithmetic and it becomes obvious where the numbers come from.

A 24-bit channel — a bus width divisible by three

Memory bus widths have long been powers of two. Four 16-bit channels make 64 bits, eight make 128. LPDDR6 breaks that habit. With one channel at 24 bits, two channels make 48 bits and four make 96. Tom's Hardware summed it up as a "non-power-of-two transfer size means weird divisible-by-3 memory bus widths."

Why that is inconvenient is a system-design problem. Existing SoC memory controllers, interconnects, and cache line structures all assume power-of-two widths, so accommodating a 96-bit configuration means reworking internal data paths. It is a plausible reason the gap between standard publication and shipping silicon could run longer than usual.

The payoff is substantial. At the same pin speed, 1.5 times the width is 1.5 times the bandwidth. For a high-speed interface bumping against signal-integrity limits, widening the bus is the surest way to gain bandwidth without pushing frequency higher.

How much faster is LPDDR6 than LPDDR5X?

Theoretical bandwidth comes from a single multiplication: data rate (MT/s) × channel width (bits) ÷ 8 gives bytes per second per channel. The table below feeds each generation's published figures straight into that formula.

The 6.4 Gbps LPDDR5 figure, the 8.5 Gbps LPDDR5X figure, and the 9,600 Mbps implementation on a 3nm process all come from Synopsys, while JEDEC raising the LPDDR5X ceiling to 8,533 MT/s was reported by Tom's Hardware. The bandwidth column is calculated directly from the formula above.

The ratios: LPDDR6's low end (32.00 GB/s) is 1.87 times the LPDDR5X spec ceiling (17.07 GB/s). Its high end (43.20 GB/s) is 2.53 times that same baseline, and still 2.25 times a shipping 9,600 MT/s implementation (19.20 GB/s). "Double" is not marketing inflation — it is the conservative, low-end figure.

The easy thing to miss is that the speed multiple and the bandwidth multiple are different numbers. 14,400 against 8,533 is 1.69x, but bandwidth is 2.53x. The gap of 1.5x is exactly the width ratio, 24 divided by 16. Comparing only the Gbps line on a spec sheet throws away half the story.

LPDDR6's gain is 1.69 times the speed multiplied by 1.5 times the width — read only the Gbps cell on the spec sheet and half that multiplication disappears.

12-bit sub-channels and a 32-byte access granularity

Each 24-bit channel divides into two independently operating 12-bit sub-channels. According to a breakdown of JESD209-6, each sub-channel supports 32-byte and 64-byte transfers, with a minimum access granularity of 32 bytes.

Why split at all? For moving large contiguous blocks, wider is always better. But for workloads made of many small scattered requests, a wide channel is waste. If the minimum access is 64 bytes and only 32 are actually needed, half the transfer is thrown away. Independent sub-channels let two requests proceed at once, raising concurrency and cutting latency.

On-device AI inference is exactly that kind of mixed workload — long sequential weight reads interleaved with short sporadic requests. Widening the bus without shrinking the access unit would have left much of the gain on the table.

One more low-power mechanism sits on top: a dynamic efficiency mode that keeps a single sub-channel awake and idles the rest when bandwidth demand is low. Tom's Hardware describes it as "memory shutdown during low-bandwidth periods," alongside dynamic burst length switching. How RAM speed and timing translate into real time units follows the same reasoning as an earlier piece converting RAM timing notation into nanoseconds.

New reliability entries on the spec sheet

Several features are new or newly mandatory in LPDDR6. Based on the published specification:

In one sentence: safeguards that took hold in server DRAM first have now come down to mobile DRAM. PRAC belongs to the family of countermeasures against rapidly reopening one row to disturb data in adjacent rows, and memory region isolation sits in the same context. As the nature of what a single phone processes changed, so did the bar it has to clear.

What to check on the spec sheet

Worth waiting — if on-device AI is your primary use case and you keep devices for a long time, a bandwidth multiple that starts at 1.87x is a legitimate reason to skip a generation. That said, the interval between publication and mass-production adoption cannot be fixed from public information, so check the standard name the manufacturer actually prints on the product.

Fine to buy now — if the real bottleneck on a current LPDDR5X device is storage speed or thermal throttling rather than memory bandwidth, one memory generation will not change what you feel. That is why the storage spec deserves a look alongside the RAM line.

• Whether the sheet says LPDDR5X or LPDDR6 — a listing with capacity but no generation is not a basis for judgment
• The stated data rate in MT/s or Gbps — even within LPDDR5X, 6,400 versus 8,533 is a 1.33x bandwidth difference
• Channel configuration, meaning total bus width — per-channel bandwidth times channel count is the actual system figure
• Stated RAM capacity against the minimum requirement for AI features — bandwidth and capacity are separate constraints

Sources

• JEDEC Releases New LPDDR6 Standard — JEDEC
• JEDEC publishes first LPDDR6 standard — Tom's Hardware
• LPDDR6 Explained: JEDEC JESD209-6 Speeds and Architecture
• LPDDR5X Explained: Speed and Specification — Synopsys
• LPDDR5X Memory Extends Speeds to 8533 MT/s — Tom's Hardware