A DDR5-6000 CL30 kit has a true first-word latency of exactly 10 nanoseconds. CL 30 is not a unit of time — it is a count of clock cycles — so the same CL means different durations at different speeds. DDR5-4800 CL40 works out to 16.7 nanoseconds; DDR5-8000 CL38 to 9.5. The second one has the higher CL number and is still faster.
A memory kit's name carries two numbers that point in opposite directions: the 6000 should be high, the 30 should be low. Comparing kits means collapsing both into one figure, and the collapse is a single division.
CL becomes time only after you divide by speed
The formula, as laid out by TechCompare's RAM latency calculator, is: latency (ns) = (CL x 2000) / data rate (MT/s). The constant 2000 appears because DDR transfers data twice per clock cycle.
The common confusion is what the 6000 in DDR5-6000 measures. It is transfers per second (MT/s), not clock frequency. The actual clock is half that — 3000 MHz — so one cycle lasts about 0.333 nanoseconds. Waiting 30 cycles gives 0.333 x 30 = 10 nanoseconds, matching the formula.
This matters because raw CL numbers break down across generations. DDR4-3200 CL16 computes to (16 x 2000) / 3200 = 10 nanoseconds, identical to DDR5-6000 CL30. The CL nearly doubled, but so did the speed. DDR5's larger CL figures reflect shorter cycles, not worse memory.
True latency and bandwidth across common DDR5 kits
The table applies the formula to widely sold configurations and adds theoretical dual-channel bandwidth, calculated as data rate x 8 bytes x 2 channels / 1000.
| Specification | CL | True latency (ns) | Dual-channel bandwidth (GB/s) |
|---|---|---|---|
| DDR5-4800 (JEDEC baseline) | 40 | 16.7 | 76.8 |
| DDR5-5600 | 28 | 10.0 | 89.6 |
| DDR5-6000 | 30 | 10.0 | 96.0 |
| DDR5-6000 | 36 | 12.0 | 96.0 |
| DDR5-6400 | 32 | 10.0 | 102.4 |
| DDR5-7200 | 34 | 9.4 | 115.2 |
| DDR5-8000 | 38 | 9.5 | 128.0 |
Read the columns and the two axes clearly diverge. True latency clusters between 10.0 and 9.5 nanoseconds from 5600 CL28 all the way to 8000 CL38 — a 5% spread. Bandwidth over the same range runs from 89.6 to 128.0 GB/s, a 43% spread. What premium kits sell is bandwidth, not lower latency.
Within the same 6000 speed, CL30 and CL36 differ by 2 nanoseconds, or 20%, while bandwidth is identical at 96.0 GB/s. If the two are priced close, latency is the only thing separating them. DDR5-4800 CL40 stands apart at 16.7 nanoseconds — more than 60% slower than everything else on the list.
A lower CL is better, but without knowing the speed you cannot tell whether a CL is low at all.
DDR5-6000 CL30 or 6400 CL32 — which is actually faster?
By formula, both land on exactly 10.0 nanoseconds. Bandwidth favors the 6400 kit at 102.4 GB/s, 6.7% higher. On paper the 6400 wins. Then the platform intervenes.
| Configuration | True latency (ns) | Bandwidth (GB/s) | AMD AM5 sync ratio | Character |
|---|---|---|---|---|
| DDR5-6000 CL30 | 10.0 | 96.0 | Holds 1:1 | Default target |
| DDR5-6000 CL36 | 12.0 | 96.0 | Holds 1:1 | Budget pick |
| DDR5-6400 CL32 | 10.0 | 102.4 | Usually drops to 1:2 | Intel-friendly |
| DDR5-8000 CL38 | 9.5 | 128.0 | Forced 2:1 | Enthusiast tuning |
Kingspec's DDR5 CL guide names 6000 CL30 as the reference point for both Intel LGA 1700/1851 and AMD AM5. Intel's memory controller is comparatively permissive and can convert speeds above 6400 into real gains; Ryzen behaves differently.
Why DDR5-8000 CL38 can be slower on Ryzen
According to Unibetter's analysis, pushing past 6000 MT/s on AM5 frequently drops the memory controller clock (UCLK) to half the memory clock — a desynchronized 1:2 ratio. At that moment, latency the formula never accounted for is added.
DDR5-6000 runs an actual 3000 MHz clock, and that is roughly the ceiling the Ryzen 7000/9000 memory controller tracks reliably. At 6200 or 6400 the controller often abandons 1:1; at 8000 the split is effectively mandatory. The 9.5 nanoseconds in the table is the response time of the memory chip, not the time it takes the CPU to receive the data.
The same source compares 6400 MT/s CL40 against 6000 CL30 — 12.5 versus 10 nanoseconds, a 25% latency penalty — as a case of a kit that raised only the speed number. On Intel, roughly 7200 MT/s is cited as the practical ceiling. The gap between a spec sheet and felt performance follows the same shape as the conditions under which Gen4 and Gen5 SSD sequential speeds stop mattering.
Without XMP or EXPO, you are running 4800 CL40
Based on published specifications, the 6000 CL30 printed on the box is not a JEDEC standard — it is a manufacturer-validated overclock profile, stored as XMP on Intel-oriented kits and EXPO on AMD-oriented ones. Unless it is enabled in the BIOS, the board runs JEDEC defaults.
DDR5's JEDEC baseline is 4800 CL40, or 16.7 nanoseconds. Buying 6000 CL30 and leaving the profile off raises latency by 67% and cuts bandwidth from 96.0 to 76.8 GB/s, a 20% loss. When a fresh build underperforms, this is the first setting to check.
Module layout is a second variable. Unibetter notes that two 16GB modules preserve signal integrity and timing headroom better than four 8GB modules. Filling every slot loads the memory controller enough that the same kit may fail to hold its profile.
Who each configuration fits
- Ryzen 7000/9000 builds: 6000 CL30 is the reference. It is the band where 1:1 synchronization holds, so higher numbers tend to cancel themselves out
- Recent Intel platforms: 6400 CL32 and above can convert bandwidth into real gains, at identical true latency to 6000 CL30
- Tight budgets: 6000 CL36 still lands at 12.0 nanoseconds, 28% faster than 4800 CL40. Trading CL30 for more capacity is defensible
- Video editing or large compiles: read the GB/s column before the latency column
- Adding memory to an older board: confirm profile support first, or the kit runs at 4800 CL40
- If CPU model naming is the bigger puzzle, start with how Core Ultra suffixes and power ratings are read